1. Field of the Invention
This invention relates to materials and processes for thin film deposition, and in particular, selective thin film deposition, on solid substrates.
This invention also relates to methods and materials for making conformal films for fabrication of devices in the areas of microelectronics and optics.
This invention also relates to materials and processes for producing improved porous dielectric materials used in the insulation of electrical conductors in microelectronic devices.
2. Description of the Related Art
Atomic layer deposition (also known as atomic layer epitaxy) is a process for depositing thin layers of solid materials from two vapor precursors. The surface of a substrate onto which film is to be deposited is exposed to a dose of vapor from one precursor to deposit a monolayer; then, any excess unreacted vapor from that precursor is pumped away. Next, a vapor dose of the second precursor is brought to the surface and allowed to react with the monolayer of the first precursor. This cycle of steps can be repeated to build up thicker films. One particularly important aspect of this process is that the atomic layer deposition reactions are self-limiting, in that only a certain maximum thickness can form in each cycle, after which no further deposition occurs during that cycle, even if excess reactant is available. Because of this self-limiting character, these deposition reactions produce coatings with highly uniform thicknesses. Uniformity of atomic layer deposition film thicknesses extends not only over flat substrate surfaces, but also into narrow holes and trenches. This ability of atomic layer deposition to make conformal films is called “good step coverage.”
One disadvantage of the existing atomic layer deposition process is its slow deposition rate, at typically less than 0.1 nanometer (nm) per cycle. Generally accepted theories regarding atomic layer deposition state that deposition rates cannot be larger than about 0.2 nm per cycle. These slow rates mean very low productivity, which has meant that atomic layer deposition is too expensive for most potential applications. Previously known reactions for the atomic layer deposition of silica are particularly slow, requiring more than one minute to complete a reaction cycle. See S. M. George et al., Appl. Surf. Sci. 82/83, 460 (1994); W. Gasser, Y. Uchida, M. Matsumura, Thin Solid Films 250, 213 (1994); S. Morishita, W. Gasser, K. Usami, M. Matusmura, J. Non-Crystalline Solids 187, 66 (1995); K. Yamaguchi, S. Imai, N. Ishitobi, M. Takemoto, H. Miki, M. Matsumura, Appl. Surf. Sci. 130-132, 202 (1998); J. W. Klaus, O. Sneh, A. W. Ott and S. M. George, Surface Review and Letters 6, 435 (1999); J. D. Ferguson, A. W. Weimer and S. M. George, Applied Surface Science 162-163, 280 (2000); J. D. Ferguson, A. W. Weimer and S. M. George, Chem. Mater. 12, 3472 (2000); J. W. Klaus, S. M. George, Surf. Sci. 447, 81 (2000).
Another disadvantage of existing atomic layer deposition processes is that the deposited film forms indiscriminately on all exposed surfaces. While substrate masking may avoid deposition in certain areas, it is not always convenient or possible to integrate masking into the fabrication process. The ability to selectively deposit a film of uniform thickness would be highly attractive in many device fabrication processes.
Silica has remained the dielectric material of choice in microelectronics for much of the past four decades. However, as the sizes of microelectronic devices have become progressively smaller, and integrated circuits are reduced in size to deeper sub-micron dimensions, signal propagation delay, electrical cross talk between conductors, and power consumption are greatly increased due to parasitic capacitance and resistance. As transistors shrink and the total amount of interconnect wiring increases, delays in that wiring greatly impact circuit performance. As wires become closer together and operating frequencies climb, cross talk between adjacent lines can degrade signal integrity. A better insulator, i.e., one with a lower k value, between the wires or active device regions reduces this noise. Therefore, there has been a strong demand for low-k inter-metal dielectric materials instead of conventional silica. Further decreases in k values (to below a value of about 2.6) are believed necessary to meet the device performance and power dissipation requirements of microelectronic devices of the future.
Reaching such low-k values generally involves reducing the density of chemical bonds, either by reducing the material density or introducing porosity. A variety of methods currently exist for making porous ultra-low k materials with pore diameters typically in the range from about 1 to about 10 nm. Examples of porous low-k materials include hydrogen silsesquioxane, methyl silsesquioxane, aerogels, xerogels, SiCxOHy, SiLK® (Dow Chemical), CORAL® (Novellus), Black Diamond® (Applied Materials), and CVD-deposited methyl silanes, etc. These materials have a density on the order of 1.2 grams/cc or less.
The porous nature of these low-k porous dielectric materials presents special structural challenges when they are integrated into microelectronic devices. For example, interconnections between the pores open up diffusion pathways through the ultra-low-k material. Metal atoms from both a barrier metal layer and conductive interconnections may diffuse into the porous insulating material layer. Such diffusion of metal atoms into the porous dielectric layer can lead to excessive leakage currents between other conductive interconnections and lead to a breakdown of the insulating characteristics of the insulating layer. Standard deposition techniques such as atomic layer deposition that deposit an electrically conductive diffusion barrier onto a low-k or ultra low-k material may result in deposition of conducting material inside the pores and can even introduce electrical short circuits through the low-k insulator. See, for example, W. Besling, et al. in Atomic Layer Deposition of Barriers for Interconnect, International Interconnect Technology Conference 2002. In addition, another problem that typically results from the use of porous dielectric materials is that openings formed in such materials have relatively rough sidewalls due to the porous nature of the insulating material. This may create problems in filling the opening with an appropriate conductive metal and undesirable voids, gaps or seams may be created in between the sidewall of the dielectric and the conductive metal.
Thus, what are needed are materials and methods for preserving the desired low-k attributes of porous insulating materials while reducing some or all of the aforementioned problems associated with porous structures.
Another place in which low-k dielectric materials are needed in microelectronic devices is in the trenches that isolate one electrically active region from adjacent ones. In current technology, silica is deposited in these trenches by chemical vapor deposition induced by a high-density plasma. See, for example, U.S. Pat. No. 6,335,288, which shows that this deposition method is limited to trenches with aspect ratios (depth/width) less than 6:1. Devices could be made on smaller areas of silicon if there were methods for filling narrower trenches (higher aspect ratios) with a dielectric, and even more advantageously with a dielectric having a dielectric constant lower that that of silica.
Another difficulty with currently used methods for filling isolation trenches is that the dielectric is also deposited on top of the flat surfaces between the trenches. This material on top then must be removed by a process called chemical-mechanical polishing (CMP). CMP is prone to remove more material in the regions just over the trench, so that the final polished surface is non-planar (“dished”). Dishing during CMP can be avoided by the use of an additional photolithographic step, which adds complexity and cost to the process. Alternatively, additional polish stop layers, sacrificial dielectric layers and etching steps can be used to avoid dishing. See U.S. Pat. No. 6,342,432. It would be highly advantageous be able to fill trenches while avoiding the unwanted deposition of dielectric material on the surfaces outside of the trenches.
Another function of the material deposited inside isolation trenches is to prevent the undesired diffusion of boron and oxygen through the dielectric. Since these elements diffuse readily through silica, a layer of silicon nitride is often required within the trench as a diffusion barrier. See U.S. Pat. No. 6,339,004 and U.S. Patent Application 2002/0004281 for a description of the use of additional silicon nitride layers to prevent diffusion. It would be advantageous to have a process in which the low-k dielectric itself is a sufficient barrier to the diffusion of boron, oxygen or other undesired elements.